| Title: | GS1-5 An FPGA-based cortical and thalamic silicon neuronal network |
|---|---|
| Publication: | ICAROB2016 |
| Volume: | 21 |
| Pages: | 134-137 |
| ISSN: | 2188-7829 |
| DOI: | 10.5954/ICAROB.2016.GS1-5 |
| Author(s): | Takuya Nanami, Takashi Kohno |
| Publication Date: | January 29, 2016 |
| Keywords: | silicon neuronal network, neuron model, FPGA, cortex, thalamus |
| Abstract: | A DSSN model is a neuron model which is designed to be implemented efficiently by digital arithmetic circuit. In our previous study, we expanded this model to support the neuronal activities of several cortical and thalamic neurons; Regular spiking, fast spiking, intrinsically bursting and low-threshold spike. In this paper, we report our implementation of this expanded DSSN model and a kinetic-model-based silicon synapse on an FPGA device. Here, synaptic efficacy was stored in block RAMs, and external connection was realized based on a bus that conform to the address event representation. We simulated our circuit by the Xilinx Vivado design suit. |
| PDF File: | https://alife-robotics.co.jp/members2016/icarob/data/papers/GS/GS1-5.pdf |
| Copyright: | © The authors. This article is distributed under the terms of the Creative Commons Attribution License 4.0, which permits non-commercial use, distribution and reproduction in any medium, provided the original work is properly cited. See for details: https://creativecommons.org/licenses/by-nc/4.0/ |
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