| Title: | OS9-1 Implementation of Multi-FPGA Communication using Pulse-Coupled Phase Oscillators |
|---|---|
| Publication: | ICAROB2017 |
| Volume: | 22 |
| Pages: | 128-131 |
| ISSN: | 2188-7829 |
| DOI: | 10.5954/ICAROB.2017.OS9-1 |
| Author(s): | Dinda Pramanta, Takashi Morie, Hakaru Tamukoh |
| Publication Date: | January 19, 2017 |
| Keywords: | pulse-coupled oscillators, synchronization, Winfree's model, FIFO, GTX, multi-FPGA, |
| Abstract: | This paper proposes an implementation of multi-Field Programmable Gate Array (FPGA) communication using pulse-coupled phase oscillators. At first, we construct a digital phase oscillator circuit with adjustable in-phase parameters. While performing the synchronization task, the oscillators are connected into the first input and first output (FIFO) interface. The communication in-between of FPGAs will occur by enabling the following inputs and outputs on the FIFO through the Gigabit Transceiver (GTX) clock domain. Pulse-coupled phase oscillators of Winfree's model are utilized as a spike generator and we expect the ideal of model circuit will synchronize. We employ two FPGA boards of Virtex6 ML605 and implement four oscillators on a hardware level. Experimental results show that first spike synchronizing over two FPGAs takes 12.47 μsec with data bit speed stream 3.2Gbps. |
| PDF File: | https://alife-robotics.co.jp/members2017/icarob/data/html/data/OS_pdf/OS9/OS9-1.pdf |
| Copyright: | © The authors. This article is distributed under the terms of the Creative Commons Attribution License 4.0, which permits non-commercial use, distribution and reproduction in any medium, provided the original work is properly cited. See for details: https://creativecommons.org/licenses/by-nc/4.0/ |
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